Meta Design Verification Engineer Job Bangalore – Apply Now for ASIC SoC Role
Meta hiring Design Verification Engineer in Bangalore. Work on ASIC/SoC verification, debug, and cross‑team collab. Apply online now
Meta is looking for a Design Verification Engineer for its Infra Silicon team in Bangalore. This team make in‑house ASIC and SoC chips for AI/ML, video workloads in data centers – faster, more efficient and less power hungry. You will be part of the DV group, working close with design, arch, emu and silicon validation folks to make sure the chip is top quality and bug free before it goes out.
Job Description
| Company | Meta |
|---|---|
| Role | Design Verification Engineer |
| Location | Bangalore, India |
| Job Type | Full Time |
| Team | Infra Silicon – DV |
| Category | Engineering, Tech & Design – Hardware |
| Degree | Bachelor’s Degree |
| Branch | CS/Electronics |
| Apply Link | Via Meta Careers site |
What You Will Do
- Write functional tests from test plan, cover all features
- Push DV to closure using coverage metrics – functional and code both
- Debug fails, find root cause, work with design/arch team to fix
- Collab with cross teams like model, emu, silicon validation
Minimum Qualification
Bachelor degree in Electronics Engineering, Computer Engineering, CS, VLSI or similar. Must be done before joining.
Need exp in constrained‑random or coverage driven verification or C/C++ verification.
Should know IP block verification using standard DV methods.
Familiar with EDA tools and scripting (Python, TCL, Perl, Shell).
Understanding in CPU, GPU, networking, interconnects or fabrics is plus.
Preferred Qualification
Good at debugging fails to RTL line using Verdi or similar.
Know version control like Git, Mercurial, SVN.
Worked in CPU/GPU env before.
Master degree in Electronics/CS/VLSI is nice to have.
Can build SystemVerilog/UVM env from scratch.
Done verification of peripheral IPs like UART, SPI, I2C and know APB, AXI protocols.
Why Join Meta
You get to work on cutting edge ASIC/SoC projects, with top engineers, good pay and benefits. Your work will impact AI/ML workloads at huge scale. Plus, you learn end‑to‑end DV flow in real big tech env.
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